The present invention relates to a semiconductor integrated circuit device, or more in particular to a technique effectively applied to a dynamic RAM (Random Access Memory) assembled on a lead-on chip (LOC) subjected to memory access by a plurality of bits each time, for example.
Examples of dynamic RAM assembled in LOC structure are disclosed in U.S. Ser. No. 07/424,904 filed Oct. 18, 1989 and U.S. Ser. No. 07/899,572 filed Jun. 18, 1992 corresponding to JP-A-3-214669 laid open Sep. 19, 1991. The dynamic RAM disclosed in the publication is fabricated by forming a pair of leads extending longitudinally at the central portion of a rectangular semiconductor chip for supplying a ground potential VSS and a source voltage VCC, which leads are wire-bonded with a plurality of grounding pads and power pads at a plurality of points. As a result, the use of a wiring material of low resistance value such as a lead frame provides the ground potential VSS and the source voltage VCC at a plurality of points, thereby reducing the power impedance of the circuit to minimum.
In the aforementioned method of supplying an operating voltage to a semiconductor chip by the use of the LOC structure, although the power impedance of the circuit is minimized, a comparatively large power noise generated by simultaneous operation of a multiplicity of output circuits with the increase in the number of bits for memory access is liable to be propagated to other circuits including input circuits. Especially, with the decrease in the operating voltage due to lower power consumption of semiconductor integrated circuit devices and the resulting tendency toward a smaller and smaller level margin for input circuits, the power noise generated by a multiplicity of outputs poses an important problem. In addition to this problem, it has been found that it is necessary to solve the problem of what is called electrostatic discharge (ESD) in which input circuit elements are destroyed by a substrate surge due to the power supply. See for example, "A New On-chip ESD Protection Circuit with Dual Parasitic SCR Structures for CMOS VLSI", IEEE Journal of Solid State Circuit, Vol. 27, No. 3, March 1992, pp. 274-280.